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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1997 jun 13 integrated circuits SAA8110G digital signal processor (dsp) for cameras
1997 jun 13 2 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G features high precision digital processing with 9 or 10 bit input different types of ccds (pal, ntsc and cif) (progressive, interlaced and non-interlaced) black offset preprocessing (including optical black offset control) rgb-separation (with contour and white clip signals generation) rgb-processing (colour space matrix, black control, knee and gamma) rgb-to-yuv conversion (including down-sampling ?lters) white balance control y-processing (contour processing, false colour detector, ?lters and noise reduction) uv-processing (false colour correction and noise reduction) digital output formatter (including cif-formatter, dtv2, d1) analog output preprocessing (including pal/ntsc-encoder and dacs) measurement engine (prepared for auto-exposure and auto-white balance features) miscellaneous functions (e.g. switched mode power supply pulse generator, control dac) vh-reference and window timing serial interface (selectable i 2 c-bus or 80c51 uart interface) mode control (including power management). applications desktop video applications surveillance systems video-phone systems. general description the SAA8110G is designed for desktop video applications (teleconferencing, video grabbing), surveillance and video-phone systems. the SAA8110G may be applied together with an analog front-end (tda8786 including cds/agc/adc), a timing generator and a microcontroller as shown in figs 18 and 19. other configurations are also possible. the ccd-sensor can be of pal, ntsc or cif type (with complementary mosaic colour filter). the maximum number of active pixels is limited to 800 samples/line. the 10-bits digital input may have a pixel frequency of up to 14.318 mhz. the SAA8110G output data is available in a digital and an analog output format. two digital output formats are selectable: dtv2 (ccir-601 at the input pixel frequency) and d1 (ccir-656 at twice the input pixel frequency). it is also possible to generate the cif and qcif formats as subsets from the processed ccd-image. the analog output is available in one of four formats: rgb, yuv, yc or cvbs. the SAA8110G includes a digital pal/ntsc-encoder and 3 dacs for this purpose. two types of serial interface are selectable: a fast 400 khz i 2 c-bus interface or a 80c51 uart interface (with bit rates from 1 mbit/s up to 3.75 mbit/s depending on the system clock used). the power dissipation of the SAA8110G can be optimized for each application using the built-in power management function. ordering information type number package name description version SAA8110G lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm sot315-1
1997 jun 13 3 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G quick reference data note 1. when digital mode is selected, v dda supply pins can be connected to ground. symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 3 5 5.25 v v dda analog supply voltage 3 5 5.25 v v il low level digital input voltage 0 - 0.3v ddd v v ih high level digital input voltage 0.6v ddd - v ddd v v ol low level digital output voltage i ol = - 20 m a -- 0.5 v v oh high level digital output voltage i oh = 20 m av ddd - 0.1 -- v i ddd(tot) total digital supply current f clk = 14.3 mhz; v ddd =5v - 180 200 ma f clk = 14.3 mhz; v ddd = 3.3 v - 80 100 ma i dda(tot) total analog supply current f clk = 14.3 mhz; v dda =5v - 30 40 ma f clk = 14.3 mhz; v dda = 3.3 v - 22 35 ma t amb operating ambient temperature 0 - 75 c i dmd supply current in digital output mode f clk = 14.3 mhz; v ddd =5v; note 1 - 185 - ma f clk = 14.3 mhz; v ddd = 3.3 v - 85 - ma
1997 jun 13 4 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G block diagram f ull pagewidth mgk158 7 to 16 ccd9 to ccd0 clk1 v ddd(c1) v ddd(c2) v ddd(c3) v ddd(p1) v ddd(p2) v ssd(c1) v ssd(c2) v ssd(c3) v ssd(c4) v ssd(p1) v ssd(p2) v dda(bg) v dda(dc) v dda(cd) v dda(o1) v dda(o2) v dda(o3) v ssa(cd) v ssa(ob) v ssa(bg) 1, 29,72, 46, 62 6, 17, 76, 78, 53, 71 45, 41, 22, 40, 38, 36 19, 34, 42 offset pre- processing rgb separation (incl. line memories) rgb processing digital output formatter analog output preprocessing pal/ntsc- encoder v dacs y- processing uv- processing rgb to yuv 2 clk2 47 reset 31 to 33 t2, t1, t0 mode control miscellaneous functions SAA8110G measurement engine 30 20 21 25 26, 27 23 24 18 sclk cdac out cdac rbias sdata strobe smp p0, p1 vh-reference window timing and control 345 fi in 73 77 75 74 vsync in hsync in scl/sn cl sda a0/sn da a1/sn res snert/i 2 c interface snert/ i 2 c select y0 to y7 uv0 to uv7 70 to 63 43 vsync out 44 href 28 80 49 50 48 52 51 61 to 54 out3 to out1 decoupl rbias sis 79 x in x out 35, 37, 39 llc cref/pxq fi out fig.1 block diagram.
1997 jun 13 5 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G pinning symbol pin i/o description v ddd(c1) 1 i digital supply 1 for digital core and clk1 related peripherals clk1 2 i system- or pixel clock vsync in 3 i vertical synchronization input hsync in 4 i horizontal synchronization input fi in 5 i ?eld identi?cation signal input v ssd(c1) 6 i digital ground 1 for digital core and clk1 related peripherals ccd9 7 i (preprocessed) ad-converted cdd-signal bit 9 (msb) ccd8 8 i (preprocessed) ad-converted cdd-signal bit 8 ccd7 9 i (preprocessed) ad-converted cdd-signal bit 7 ccd6 10 i (preprocessed) ad-converted cdd-signal bit 6 ccd5 11 i (preprocessed) ad-converted cdd-signal bit 5 ccd4 12 i (preprocessed) ad-converted cdd-signal bit 4 ccd3 13 i (preprocessed) ad-converted cdd-signal bit 3 ccd2 14 i (preprocessed) ad-converted cdd-signal bit 2 ccd1 15 i (preprocessed) ad-converted cdd-signal bit 1 ccd0 16 i (preprocessed) ad-converted cdd-signal bit 0 (lsb) v ssd(c2) 17 i digital ground 2 for digital core and clk1 related peripherals sclk 18 o serial clock to tda8786 v ssa(cd) 19 i analog ground for control dac cdac out 20 o output control dac cdac rbias 21 i pin to connect external bias resistor for control dac v dda(cd) 22 i analog supply for control dac sdata 23 o serial data to tda8786 strobe 24 o strobe to tda8786 smp 25 o switch mode pulse for dc-dc p0 26 o quasi-static control output pin 0 p1 27 o quasi-static control output pin 1 sis 28 i snert/i 2 c-bus select input signal v ddd(c2) 29 i digital supply 2 for digital core and clk1 related peripherals reset 30 i reset input t2 31 i test mode control signal bit 2 t1 32 i test mode control signal bit 1 t0 33 i test mode control signal bit 0 v ssa(ob) 34 i analog ground for the three output buffers out3 35 o output buffer 3 (r, v or cvbs) v dda(o3) 36 i analog supply for output buffer out3 out2 37 o output buffer 2 (b, u or c) v dda(o2) 38 i analog supply for output buffer out2 out1 39 o output buffer 1 (g or y) v dda(o1) 40 i analog supply for output buffer out1
1997 jun 13 6 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G v dda(dc) 41 i analog supply for analog core of triple dac v ssa(bg) 42 i analog ground for to band gap decoupl 43 o pin to be used for external decoupling of band gap rbias 44 o external bias resistor connection for band gap v dda(bg) 45 i analog supply for band gap v ddd(p1) 46 i digital supply 1 for clk2 related peripherals clk2 47 i output clock (clk2 frequency is 2 clk1 frequency) fi out 48 o ?eld identi?cation output pulse vsync out 49 o vertical synchronization output href 50 o horizontal reference output for yuv-port cref/pxq 51 o clock/pixel quali?er output for yuv-port llc 52 o line-locked system clock output v ssd(p1) 53 i digital ground 1 for clk2 related peripherals uv7 54 o multiplex chrominance uv bit 7 (msb) uv6 55 o multiplex chrominance uv bit 6 uv5 56 o multiplex chrominance uv bit 5 uv4 57 o multiplex chrominance uv bit 4 uv3 58 o multiplex chrominance uv bit 3 uv2 59 o multiplex chrominance uv bit 2 uv1 60 o multiplex chrominance uv bit 1 uv0 61 o multiplex chrominance uv bit 0 (lsb) v ddd(p2) 62 i digital supply for clk2 related peripherals y7 63 o luminance y or multiplexed yuv bit 7 (msb) y6 64 o luminance y or multiplexed yuv bit 6 y5 65 o luminance y or multiplexed yuv bit 5 y4 66 o luminance y or multiplexed yuv bit 4 y3 67 o luminance y or multiplexed yuv bit 3 y2 68 o luminance y or multiplexed yuv bit 2 y1 69 o luminance y or multiplexed yuv bit 1 y0 70 o luminance y or multiplexed yuv bit 0 (lsb) v ssd(p2) 71 i digital ground 2 for to clk2 related peripherals v ddd(c3) 72 i digital supply 3 for digital core and clk1 related peripherals a1/sn res 73 i i 2 c-bus address select pin a1 or snert reset input a0/sn da 74 i i 2 c-bus address select pin a0 or snert data input/output sda 75 i i 2 c-bus data input/output v ssd(c3) 76 i digital ground 3 for digital core and clk1 related peripherals scl/sn cl 77 i i 2 c-bus clock/snert clock input v ssd(c4) 78 i digital ground 4 for digital core and clk1 related peripherals x in 79 i input crystal oscillator for subcarrier lock applications x out 80 o output crystal oscillator for subcarrier lock applications symbol pin i/o description
1997 jun 13 7 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.2 pin configuration. handbook, full pagewidth SAA8110G mgk151 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 uv1 uv2 uv3 uv4 uv5 uv6 uv7 v ssd(p1) llc cref/pxq href vsync out fi out clk2 v ddd(p1) v dda(bg) rbias decoupl v ssa(bg) v dda(dc) v ddd(c1) clk1 vsync in hsync in fi in v ssd(c1) ccd9 ccd8 ccd7 ccd6 ccd5 ccd4 ccd3 ccd2 ccd1 ccd0 v ssd(c2) sclk v ssa(cd) cdac out 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 x out x in v ssd(c4) scl/sn cl v ssd(c3) sda a0/sn da a1/sn res v ddd(c3) v ssd(p2) y0 y1 y2 y3 y4 y5 y6 y7 v ddd(p2) uv0 cdac rbias v dda(cd) sdata strobe smp p0 p1 sis v ddd(c2) reset t2 t1 t0 v ssa(ob) out3 v dda(o3) out2 v dda(o2) out1 v dda(o1)
1997 jun 13 8 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G functional description black offset preprocessing the input data is clamped within the optical black pixel area of the ccd. the size of the digital clamp window is 16 pixels by 128 lines (i.e. tda8786). it is possible to differentiate black levels for odd/even lines, pixels and fields. this comes in addition to the analog preprocessing clamp which is active on the clamp pulse generated by the external timing circuit. the analog clamp is included in the tda8786. rgb separation pal/ntsc sensors generate interlaced data adding offset in the complementary colour pixels. the rgb separation block with its two line memories generates the three components y, 2r - g, and 2b - g for each input data corresponding to a pixel value of the ccd. then the triplet r, g, b is derived. this block also delivers some contour and white clip information. rgb processing the rgb processing includes several features: colour space matrix depending on ccd type to be suitable with different sensor colour filters gain correction for r and b signals for white balance control black offset adjustable knee adjustable gamma function. the knee function is applied to all three rgb signals. its shape is continuously adjustable by changing the slope and the knee offset point. to compensate for the non-linear response of display devices, a gamma correction is applied to r, g and b signals. it may be adjustable from linear to a 0.35 power coefficient. fig.3 rgb separation diagram. handbook, full pagewidth mgk153 line memory line memory r g b ccd inputs white clip vertical contour rgb colour separation 10 fig.4 rgb processing. handbook, full pagewidth mgk154 colour matrix r r gain r black g black g b 3 knee r g b + + b gain b black + 3 gamma
1997 jun 13 9 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G rgb-to-yuv block after rgb processing, the channels are separated in a luminance and two colour difference path: y = 0.299 r + 0.597 g + 0.114 b, u = 0.49 (b - y) and v = 0.88 (r - y) . it also contains two down-sampling filters for u and v signals. y-processing the luminance component includes several features: contour correction allowing an increase of the luminance transitions for a sharper picture black stretch function for contrast enhancement in dark scenes false colour detector used by the uv-processing block to enable the colour killer filters and noise reduction by coring (only in the high frequency part of the signal). fig.5 rgb-to-yuv conversion. handbook, full pagewidth mgk155 y (0 to 511) conversion matrix down- sampling & mux 9 r g b uv ( - 128 to 127) 8 fig.6 y processing. handbook, full pagewidth mgk156 noise reduction contour processing and false colour detection black stretch false colour y (0, 0.5 to 255.5) y 8 + 9 vertical contour ( - 512 to 511) (from rgb-separation) 10
1997 jun 13 10 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.7 uv-processing. handbook, full pagewidth mgk157 uv gain control false colour correction noise reduction false colour (from y-processing) white clip (from rgb-separation) uv ( - 127 to 128) 8 uv ( - 127 to 128) 8 uv-processing the chrominance component includes several features: noise reduction for high frequencies false colour correction: a colour killer cuts the false colour components in the uv signals uv-gain control used to set the correct uv levels for pal/ntsc encoding. as the colour filter saturation levels may be different in the ccd, the white clip is used in the uv-processing to suppress colour errors in case of high exposure . digital output formatter this block contains several features: generation of a synchronous clock llc (twice the clock frequency) generation of three synchronization signals (href, cref and vs) synchronization of the output data to the output clock llc generation of a cif/qcif output format for several type of sensors (see table 1) selection of the required digital output format (8-bit multiplexed yuv standard d1/ccir 656, including the generator of sav/eav codes or 16-bit multiplexed yuv 4:2:2 standard dtv2/ccir601). note that the d1 frequency data rate is twice the dtv2 frequency data rate. moreover, using a high resolution pal and ntsc ccds, it is possible to generate the following formats by means of cutting or down-sampling. cif 352 288 at 25 frame/second and cif 352 240 at 30 frame/second qcif 176 144 at 25 frame/second and qcif 176 120 at 30 frame/second. table 1 cif/qcif output format for different sensor types input format output format pal/ntsc-sensor cif full screen cif zoom-by-2 qcif full screen qcif zoom-by-2 qcif zoom-by-4 cif qcif full screen qcif zoom-by-2
1997 jun 13 11 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.8 vertical timing ntsc odd field. handbook, full pagewidth mgk159 hsync in vsync in fi in fi out vsync out csync blank burst 52152352524681012141820 5225241357911131519212223 fig.9 vertical timing ntsc even field. handbook, full pagewidth mgk160 hsync in vsync in fi in fi out vsync out csync blank burst 258 260 262 264 266 268 270 272 274 276 280 282 259 261 263 265 267 269 271 273 275 277 281 283 284 285
1997 jun 13 12 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.10 vertical timing pal odd field. handbook, full pagewidth hsync in vsync in fi in fi out vsync out csync blank burst (1) even frame odd frame -+ +-+-+- + -+-+-+ +- 62162262362462524681012142022 135791113152 1232425 mgk161 odd frame ++- even frame +-+- +- +-+-+- +- (1) +: burst phase = +135 . - : burst phase = - 135 . fig.11 vertical timing pal even field. (1) +: burst phase = +135 . - : burst phase = - 135 . handbook, full pagewidth hsync in vsync in fi in fi out vsync out csync blank burst (1) odd frame -+ +-+-+- + -+-+-+ +- 308 309 310 311 312 314 316 313 315 317 318 319 320 321 332 334 336 333 335 337 322 324 326 323 325 327 mgk162 even frame +-+- +- +-+-+- +- +-+
1997 jun 13 13 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.12 horizontal timing for non-cif processing. handbook, full pagewidth mgk163 0 npix hsync in href blank burst fig.13 8-bits multiplexed format (d1, ccir656); example: cif down-sampling. handbook, full pagewidth mgk164 SAA8110G (outputs clocked at clk2) host llc yuv pxq href vsync out llc y(uv) ff 00 00 sav u 0 y 0 v 0 y 2 u 4 y 4 v 4 y 6 pxq href sample moment y(uv)7 to y(uv)0
1997 jun 13 14 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.14 8-bits multiplexed format (d1, ccir656); sav/eav included. handbook, full pagewidth SAA8110G (outputs clocked at clk2) host llc y(uv)7 to y(uv)0 yuv mgk165 pxq href vsync out llc yuv ff 00 00 sav ff 00 00 eav u 0 y 0 v 0 y 1 u 2 y 2 v 2 u n - 1 y n - 1 pxq href sample moment fig.15 16-bits multiplexed format (dtv2, ccir601). handbook, full pagewidth mgk166 SAA8110G (outputs clocked at clk2) host llc uv uv7 to uv0 y(uv) y7 to y0 cref href vsync out fi out llc y(uv) u 0 y 2 y 1 y 0 v 0 y 3 u 6 y 6 y 5 y 4 u 4 v 4 u 2 v 2 cref href sample moment uv
1997 jun 13 15 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G analog output preprocessing this block contains several features: delay compensation for the luminance signal up-sampling of the uv signal pal/ntsc encoding yuv to rgb conversion selection of the required analog output format (rgb, yuv, yc or cvbs). the analog outputs are given by three voltage dacs in rgb or yuv or cvbs or yc format. channels y and g include the sync information. over-sampling at twice f clk is made so that external filtering becomes easier. it is also possible to have an adjustment of the subcarrier via the serial interface. when cvbs output is used, chrominance range is halved compared to luminance. measurement engine the measurement engine performs measurements on some selectable internal signals on frame/field basis and prepares data for auto exposure, auto focus and auto white balance processing. it uses an internal ram work-space for its control and data handling operations. the contents of the work-space can be accessed via the serial interface. vertical/horizontal reference and window timing and control the SAA8110G uses two vertical and horizontal synchronization input signals (vsync in and hsync in ) to derive internal vertical and horizontal reference signals. besides a field identification input (fi in ) signal is required. the timing of the vertical and horizontal input signals should be such that: 1. the pixel frequency (clk1) must be line-locked to the line frequency of hsync in : the number of clock periods between two hsync in pulses must be a fixed integer number. the hsync in should be at least one clock period active high. 2. the vsync in signal indicates the start of a field ( or frame in case of progressive scanning ); this signal is also required for non-interlaced applications. the vsync in should be at least one clock period high. 3. the fi in pulse indicates the phase of the field in case of interlaced applications (fi in = 0 means odd field). serial interface the serial interface can either be an i 2 c-bus or a 80c51 uart (snert) (selectable with the sis pin). via the serial interface the external microcontroller can control the internal settings of the SAA8110G and read/write from/to the internal ram work-space linked to the measurement engine (see list of parameter settings in chapter programming). some of the registers are double-buffered to prevent that the change of control data becomes visible on the output display. miscellaneous functions a three wire bus is used to send 10-bit settings from a microcontroller to the tda8786 via the SAA8110G registers.the SAA8110G supplies picture parameters and needs some configuration parameters. those values are contained in registers and are updated during every vertical synchronization pulse. mode control this block controls the operation mode of the SAA8110G. as described in table 2, four modes may be selected: depending on power reduction and i 2 c-bus timing. power dissipation management the power dissipation of the SAA8110G will depend on the required activity for a certain application. it is possible to switch off via the serial interface unconcerned parts for a given application. when an analog output is not used, the power voltage pin of the dac can be connected to ground to limit the power consumption. clock con?gurations following conditions must be fulfilled: clk1 should be generated as divide-by-two from clk2 the reset pin should not go low before clk1 and clk2 are both high or low. table 2 SAA8110G mode control t2 t1 t0 mode power reduction t o(h) i 2 c-bus 0 0 0 application mode on short 0 0 1 on long 0 1 0 off short 0 1 1 off long
1997 jun 13 16 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G table 3 sensor and output formats covered by the SAA8110G limiting values in accordance with the absolute maximum rating system (iec134). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics ccd-formats resolution pixel frequency (mhz) output formats standard frame scanning and frequency (hz) active h/v total h/v digital analog dtv2/d1 cif cif non-interlaced 60 352/243 429/262 6.75 no yes yes cif non-interlaced 50 352/288 432/312 6.75 no yes yes ntsc high resolution non-interlaced 60.054 768/243 910/262 14.3181 yes yes yes interlaced 29.997 768/494 910/525 pal high resolution non-interlaced 50 752/288 908/312 14.1875 yes yes yes interlaced 25 752/582 908/625 ntsc medium resolution non-interlaced 60 512/243 606/262 9.53495 yes no yes interlaced 30 512/492 606/525 pal medium resolution non-interlaced 50 512/288 618/312 9.65625 yes no yes interlaced 25 512/582 618/625 symbol parameter min. max. unit v ddd digital supply voltage - 0.3 +7.0 v v dda analog supply voltage - 0.3 +7.0 v d v ddd-dda supply voltage difference between the digital and the analog supply voltages - 0.1 +0.1 v v i input voltage - 0.3 v dd + 0.3 v v o output voltage - 0.3 v dd + 0.3 v p tot total allowed power dissipation at t amb =75 c - 1w t stg storage temperature - 55 +150 c t j junction temperature - 125 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 50 k/w
1997 jun 13 17 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G characteristics symbol parameter conditions min. typ. max. unit vdacs speci?cation o utputs pins out1 to out3 ( in case of scale factor =1) v o output voltage (see note 1) code 0 0 0.2 0.3 v code 511 1.3 1.5 1.6 v v offset amplitude offset voltage between dacs - 60 +60 mv i nputs r bias bias resistor note 2 14 15 16 k w note 3 44 47 50 k w r ext external anti-re?ection resistor note 2 - 21 -w note 3 - 70.6 -w c decoup decoupling capacitor 10 - 100 nf t ransfer function res resolution - 9 - bit nl diff differential non-linearity -- 1.5 lsb nl int integral non-linearity -- 1.5 lsb thd 60 total harmonic distortion at 60% of full-scale f clk = 30 mhz, f i = 1 mhz, v dda =5v - 55 45 db s/n signal-to-noise ratio f clk = 30 mhz, f o = 1 mhz, v dda =5v - 45 38 db a pplication 1: pal/ntsc high resolution v dd1 supply voltage 4.5 5.0 5.5 v v dd2 supply voltage 3.0 3.3 3.6 v cr conversion rate - 28.6 - mhz f clk clock frequency - 28.6 - mhz b a analog bandwidth - 7.6 - mhz a pplication 2: pal/ntsc medium resolution v dd1 supply voltage 4.5 5.0 5.5 v v dd2 supply voltage 3.0 3.3 3.6 v f clk clock frequency - 19 - mhz b a analog bandwidth - 6.5 - mhz s witching characteristics on rising full - scale step (see fig.16) t pd propagation delay time to 50% value - 913ns t st(10-90) settling time 10% to 90% full-scale - 911ns t st(lsb) setting time (to 1 lsb) - 25 30 ns
1997 jun 13 18 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G notes 1. when cvbs output is used the chrominance range is halved compared to luminance. 2. monitor load of 75 w with r ext =21 w and r bias =15k w at 3.3 v application. 3. monitor load of 75 w with r ext = 70.6 w and r bias =47k w at 5.0 v application. cdac speci?cation (v dd =5v) l int integral linearity -- 1 lsb l diff differential linearity -- 1 2 lsb v o(cdac) output voltage at pin cdac code 0 - 10 300 mv code 61, v dda =5v - 4.6 4.95 - v code 61, v dda = 3.3 v 3 3.25 - v r o(cdac) output resistance at pin cdac - 13 -w f clk clock frequency - 28.6 - mhz r l load resistance - 10 - k w c l load capacitance -- 10 pf t pd propagation delay time to 50% value (see fig.17), v dda =5v -- 104 ns t st(10-90) settling time 10% to 90% full-scale (see fig.16) - 9 - ns t st(lsb) setting time to 1 lsb (see fig.16) - 25 - ns i nputs related to clk1: ccd0 to ccd9, vsync in , hsync in, fi in t su(i)(d)1 data input set-up time ccd inputs, hsync in , vsync in , fi in 035ns t su(i)(d)2 data input set-up time sn res and sn da 012ns t h(i)(ccd) data hold time ccd inputs - 1 - +1 ns t h(i)(d) data input hold time vsync in , hsync in , fi in 013ns o utputs related to clk2: y7 to y0, uv7 to uv0, cref, href, vsync out ,fi out and llc t h(o)(d) data output hold time - 822ns t d(o)(d) data output delay time - 25 31 ns o utputs related to clk1: sdata, strobe, smp, p0, p1 and sclk t h(o)(d) data output hold time - 13 21 ns t d(o)(d) data output delay time - 15 24 ns d clk clock duty cycle 40 - 60 % symbol parameter conditions min. typ. max. unit
1997 jun 13 19 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.16 switching characteristics. handbook, full pagewidth clk2 (code 0) code 0 (code fs) code fs input code (example of a full-scale input data transmission) 1 lsb 1 lsb 90% 50% 10% mgk167 t pd t st(10 - 90) t st(lsb) fig.17 data input/output timing. handbook, full pagewidth mgk168 clk1 data in data out t pd t h(i)(d) t su
1997 jun 13 20 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G programming overview available write address symbol function format range/value 0 control0 miscellaneous; see table 4 byte n.a. 1 control1 miscellaneous; see table 5 (1) byte n.a. 2 control2 miscellaneous; see table 6 byte n.a. 4 ob_startl_f0 ?rst line optical black window in ?eld 0 byte 0 to 255 5 ob_startl_f1 ?rst line optical black window in ?eld 1/frame byte 0 to 255 7 ob_startp ?rst pixel optical black window byte 0 to 255 8 ob_pe_f0 ?xed optical black level for even pixel in ?eld 0 byte 0 9 ob_po_f0 ?xed optical black level for odd pixel in ?eld 0 byte 0 10 ob_pe_f1 ?xed optical black level for even pixel in ?eld 1/frame byte 0 11 ob_po_f1 ?xed optical black level for odd pixel in ?eld 1/frame byte 0 12 ob_offset_le optical black offset for even line byte 0 13 ob_offset_lo optical black offset for odd line byte 0 14 mosaic_sep_s1 multiplication-factor for yn at even line and even pixel byte 0 to 255 15 mosaic_sep_s2 multiplication-factor for yn at even line and odd pixel byte 0 to 255 16 mosaic_sep_s3 multiplication-factor for yn at odd line and even pixel byte 0 to 255 17 mosaic_sep_s4 multiplication-factor for yn at odd line and odd pixel byte 0 to 255 18 white_clip_thr threshold for white clip byte 768 to 1023 19 col_mat_p11 colour matrix coef?cient p11 byte - 128 to 127 20 col_mat_p12 colour matrix coef?cient p12 byte - 128 to 127 21 col_mat_p13 colour matrix coef?cient p13 byte - 128 to 127 22 col_mat_p21 colour matrix coef?cient p21 byte - 128 to 127 23 col_mat_p22 colour matrix coef?cient p22 byte - 128 to 127 24 col_mat_p23 colour matrix coef?cient p23 byte - 128 to 127 25 col_mat_p31 colour matrix coef?cient p31 byte - 128 to 127 26 col_mat_p32 colour matrix coef?cient p32 byte - 128 to 127 27 col_mat_p33 colour matrix coef?cient p33 byte - 128 to 127 28 col_mat_rgain colour matrix r-gain factor (1) byte 0 to 255 29 col_mat_bgain colour matrix b-gain factor (1) byte 0 to 255 34 black_level_r ?xed r-black level offset (1) byte - 128 to 127 35 black_level_g ?xed g-black level offset (1) byte - 128 to 127 36 black_level_b ?xed b-black level offset (1) byte - 128 to 127 37 rgb_knee_offset offset for rgb-knee (1) byte 0 to 255 38 gamma_balance gamma multiplication factor (ls) (1) 6 bits 0 to 63
1997 jun 13 21 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G 39 npix_lsb number of pixels on a line byte 0 to 255 40 npix_msb number of pixels on a line 2 bits 0 to 3 41 fpix_act number of ?rst active pixel on a line byte 0 to 255 42 lpix_act_lsb number of last active pixel on a line byte 0 to 255 43 fline_act_f0 number of ?rst active line in ?eld 0 byte 0 to 255 44 lline_act_f0_lsb number of last active line in ?eld 0 byte 0 to 255 45 fline_act_f1_lsb number of ?rst active line in ?eld 1/frame byte 0 to 255 46 lline_act_f1_lsb number of last active line in ?eld 1/frame byte 0 to 255 47 act_lines_msb msbs of active line numbers byte see table 7 48 ctr_upd_line number of line for double buffered update control registers byte 0 to 255 49 kcomb vertical contour comb ?lter coef?cient (ms) 3 bits 0 to 7 vcgain vertical contour gain (ls) 4 bits 0 to 15 50 cldlev contour level dependancy level (1) byte 0 to 255 51 hchgain horizontal contour band pass ?lter high gain (ms) 4 bits 0 to 15 hclgain horizontal contour band pass ?lter low gain (ls) 4 bits 0 to 15 52 cnclev contour noise coring level (1) 6 bits 0 to 63 53 congain contour gain factor byte 0 to 63 54 fcdlev false colour detect level byte 0 to 255 55 ynclev y (luminance) noise coring level byte 0 to 127 56 ygain y (luminance) gain factor (1) byte 0 57 ycmpdel y (luminance) compensation delay 4 bits - 3to4 see table 8 58 uvnclev uv (chrominance) noise coring level byte 0 to 255 59 ugain u(b - y) gain factor (1) byte 0 60 vgain v(r - y) gain factor (1) byte 0 61 dto_freq_lsb dto frequency (msb) (1) byte 0 to 255 62 dto_freq_isb dto frequency (1) byte 0 to 255 63 dto_freq_msb dto frequency (lsb) (1) byte 0 to 255 64 phaseshift phase_shift colour subcarrier byte 0 to 255 65 burst_level burst_level colour burst byte 0 to 255 66 a awb_a (me) byte - 98 pole_thresh #a (dpd) byte 0 to 255 67 b awb_b (me); pole_thresh #b (dpd) byte - 104 68 c awb_c (me); pole_thresh #a (dpd) byte - 68 69 d awb_d (me); pole_thresh #b (dpd) byte 126 70 e awb_e (me) 6 bits 63 pole_thresh #a (dpd) byte 63 71 f awb_f (me) 6 bits 0 pole_thresh #b (dpd) byte 0 72 highlightthr highlight-threshold (me); pole_thresh #a(dpd) byte 60 address symbol function format range/value
1997 jun 13 22 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G note 1. double buffered write register. 73 me_resscale me_sync + me_resultscale (me) 4 bits 0, 1 see table 9 pole_thresh #b (dpd) byte 0 to 255 74 mwhvgrid measurement horizontal and vertical grid 6 bits see table 10 78 whiteclip white clip limiter level for analog outputs byte 256 + (0 to 255) 79 auto_black auto black attack slope control 2 bits see table 20 82 dop_cntrl0 digital output processing control byte see table 11 83 dop_cntrl1 digital output processing control (1) byte see table 12 84 cif_wstrt cif-window start pixel (lsbs) byte 0 to 255 85 cif_wstrt cif-window start line (lsbs) byte 0 to 255 86 pre_si_lsb control data for analog preprocessing byte 0 to 255 87 pre_si_msb control data/address for analog preprocessing 5 bits see table 13 88 smp_cntrl control for switched mode power supply byte 0 89 pre_cntrl preprocessing/timing control byte see table 14 90 dig_setup set-up in digital output byte 0.255 91 blanklev blanking level in analog output byte 0 to 255 92 bl-setup set-up level in analog output byte 0 to 255 93 aof_cntrl analog output format control (1) byte see table 15 94 pre_proc_del control compensation delay w.i.l preprocessing 4 bits 0 to 15 126 ramwrptr write pointer for ram work-space byte 0 to 223 127 ramwrdata write data for ram work-space byte 0 to 255 address symbol function format range/value
1997 jun 13 23 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G register details table 4 control0 table 5 control1 note 1. double buffered write register. table 6 control2 note 1. double buffered write register. table 7 act_lines_msb name.bitnr name function control0.0 auto_opt_black auto optical black on/off control0.1 sens_vga rgb-bayer/complementary mosaic colour ?lter control0.2 mosaic_fil_type complementary mosaic colour ?lter control0.3 pix_phase toggle phase for pixel in colour separation control0.4 line_phase toggle phase for line in colour separation control0.5 field_phase toggle phase for ?eld in colour separation name.bitnr name function control1.2 rgb_knee_k compression factor for rgb-knee (see table 16) (1) control1.3 rgb_knee_k compression factor for rgb-knee (see table 16) (1) control1.4 med_res medium resolution for pal/ntsc encoder control1.5 pal_ntsc choose between pal/ntsc control1.6 bsscale black stretch scaling factor (see table 17) (1) control1.7 bsscale black stretch scaling factor (see table 17) (1) name.bitnr name function control2.0 fcc_filter+ false colour low-pass ?lter on/off control2.1 ni non-interlaced/interlaced control2.2 dtomwl_lsb dto measurement window length (1) control2.3 dtomwl_msb dto measurement window length (1) control2.4 wh_cl_map white clip mapping on uv-grid (see table 18) control2.5 wh_cl_map white clip mapping on uv-grid (see table 18) control2.6 fc_map false colour mapping on uv-grid (see table 19) control2.7 fc_map false colour mapping on uv-grid (see table 19) name.bitnr function act_lines_msb.0 and act_lines_msb.1 bits 8 and 9 for last active pixel number on a line act_lines_msb.2 and act_lines_msb.3 bits 8 and 9 for last active line number in ?eld 0 act_lines_msb.4 and act_lines_msb.5 bits 8 and 9 for ?rst active line number in ?eld 1/frame act_lines_msb.6 and act_lines_msb.7 bits 8 and 9 for last active line number in ?eld 1/frame
1997 jun 13 24 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G table 8 ycmpdel table 9 mecntrl table 10 mwhvgrid table 11 dop_cntrl0 content function (1+4 b3 + b2 + 2 b1 + 1 b0) t d 0000 1t d 0001 2t d 0010 3t d 0011 4t d 0100 5t d 0101 6t d 0110 7t d 0111 8t d 1000 5t d 1001 6t d 1010 7t d 1011 8t d 1100 9t d 1101 10t d 1110 11t d 1111 12t d name.bitnr function default mecnrtl.0, mecnrtl.1, mecnrtl.2 me_resultscaler selection (0, 2, 4, 8, 16, 32) 1 mecnrtl.3 me_sync (synchronize ?eld/frame toggle of measurement engine) 0 name.bitnr function default mwhvgrid.0, mwhvgrid.1, mwhvgrid.2 and mwhvgrid.3 horizontal me-window pixel size selection 4 mwhvgrid.4 and mwhvgrid.5 vertical me-window pixel size selection 4 name.bitnr function dop_cntrl0.0 and dop_cntrl0.1 horizontal cif-processing control bits hcif.0 and hcif.1 (see table 21) dop_cntrl0.2 and dop_cntrl0.3 vertical cif-processing control bits vcif.0 and vcif.1 (see table 22) dop_cntrl0.4 and dop_cntrl0.5 temporal cif-processing control bits tcif.0 and tcif.1 (see table 23) dop_cntrl0.6 cif-processing enabled/disabled (by-pass) dop_cntrl0.7 cif-format/qcif format
1997 jun 13 25 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G table 12 dop_cntrl1 table 13 pre_si_msb table 14 pre_cntrl table 15 aof_cntrl name.bitnr function default dop_cntrl1.0 and dop_cntrl1.1 horizontal pixel start msbs for cif-window - dop_cntrl1.2 and dop_cntrl1,3 vertical line start msbs for cif-window - dop_cntrl1.4 pxq-output/cref-output - dop_cntrl1.5 cif-sensor applied/non cif-sensor applied - dop_cntrl1.6 d1/d2 output format - dop_cntrl1.7 dop-processing active/disabled 1 name.bitnr function pre_si_msb.0 and pre_si_msb.1 control data bits d8 and d9 pre_si_msb.2 to pre_si_msb.4 control address bits a0 to a2 name.bitnr function pre_cntrl.0 to pre_cntrl.5 control dac-data bits 0 to 5 pre_cntrl.6 and pre_cntrl.7 static control outputs p0 and p1 name.bitnr function default aof_cntrl.0 and aof_cntrl.1 analog output format selection (see table 24) 1 aof_cntrl.2 and aof_cntrl.3 scale factor #1 for gy-multiplex (see table 25) - aof_cntrl.4 and aof_cntrl.5 scale factor #2 for bu-, c- and rv-multiplex (see table 26) - aof_cntrl.6 analog output processing active/disabled 1 aof_cntrl.7 triple dac output range control large/small - table 16 knee compression factors w 1.n compression factor n=3 n=2 00 1 8 01 1 4 10 3 8 11 1 2 table 17 black stretch scaling factors w 1.n scaling factor n=7 n=6 00 0 01 1 4 10 1 2 11 3 4
1997 jun 13 26 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G table 18 white-clip detection spreading table 19 false colour detection spreading table 20 auto black attack slope control table 21 hcif-control table 22 vcif-control w 2.n spreading filter n=5 n=4 0 0 [0 0 1 0 0] 0 1 [0 1 1 1 0] 1 x [1 1 1 1 1] w 2.n spreading filter n=7 n=6 0 0 [0 0 1 0 0] 0 1 [0 1 1 1 0] 1 x [1 1 1 1 1] w 79.n slope factor n=7 n=6 00 1 4 01 1 8 10 1 16 11 1 32 w 82.n slope factor n=1 n=0 0 0 down-sample by 4 0 1 down-sample by 2 1 x one-to-one copy w 82.n processing n=3 n=2 0 0 down-sample by 4 0 1 down-sample by 2 1 0 one-to-one copy 1 1 up-sample by 2 table 23 tcif-control table 24 analog output format selection table 25 scale #1 selection table 26 scale #2 selection w 82.n processing n=5 n=4 0 0 one-to-one copy 0 1 down-sample by 2 1 0 down-sample by 4 1 1 down-sample by 8 w 93.n format n=1 n=0 0 0 rgb 0 1 yuv 10 yc 1 1 cvbs w 93.n scale factor n=3 n=2 0x 1 10 2 11 3 2 w 93.n scale factor n=5 n=4 0x 1 10 2 11 3 2
1997 jun 13 27 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G application information tda8786 and SAA8110G can be used with sharp ccds. tda8786a and SAA8110G can be used with sony ccds. table 27 gives as an example some references of ics which may be used with philips tda8786(a)/SAA8110G. this overview is not restrictive, both devices are compatible with other ccd/v-driver/ppg combinations including the more recent ones. table 27 possible components for the application of figs 18 and 19. notes to the application diagram in the configuration of figs 18 and 19, the microcontroller reads and writes data from/to the dsp using the snert-bus (uart-mode 0). optional external control is available through the i 2 c-bus. free i/o pins of the microcontroller can be used to control pgg, or for other purposes. 83cxxx processing is synchronized by vd interruption. depending on vd polarity, it can be necessary to invert vd. a customized 83cxxx is available for this application. please contact your nearest philips sales office. ccd type component type ntsc pal medium resolution high resolution medium resolution high resolution sony ccds ccd lz2313h5 lz2353a lz2323h5 lz2363 v-driver lr36683n timing generator lz95g55 lz95g71 lz95g55 lz95g71 sharp ccds ccd icx056ak icx068ak icx057ak icx069ak v-driver cxd1250mn; cxd1267n timing generator cxd1257ar cxd1265r cxd1257ar cxd1265r
1997 jun 13 28 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.18 SAA8110G system configuration for camera application (continued in fig.19). handbook, full pagewidth p0 (optional, ppg setting) p1 (optional, ppg settings) cdac out (optional, can be used for frequency tuning) clk1 (to adc and dsp) clk2 (to dsp, clk2 = 2 clk1) cdspulse1 cdspulse2 clampcds (clamp cds, opb, adc can be the same) clampopb clampadc preblank (optional) hd (to dsp and m c) vd (to dsp and m c) fi (to dsp and m c) p0 p1 cdac out clk1 clk2 cdspulse1 cdspulse2 clampcds clampopb clampadc preblank horizontal drive vertical drive field id v4 v3 v2 v1 h1 vertical driver (ppg) h2 v4 v3 v2 v1 h1 h2 electrical shutter reset pulse ognd1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 100 nf 1 nf 1 nf 1 nf 2.2 nf 200 nf dgnd1 36 35 34 33 32 31 30 29 28 27 26 25 clpopb clk1 100 nf 100 nf 100 nf 100 nf 100 nf oen (optional) (from microcontroller) 100 nf v ddd v ddd clampcds cdspulse1 cdspulse2 pbk clampopb preblank ofdout ampout ampout agnd1 v cca1 agcout pbin pbout adcin clpadc v ref 1 2 3 4 5 6 7 8 9 10 11 12 tda8786g or tda8786ag analog to digital interface agnd3 in2 in1 v cca3 v ccd2 cdsp2 cdsp1 clpcds dgnd2 v cco oe clk dacout agnd2 v cca2 v rb sen v rt dec1 stge sclk v ccd1 stby sdata 13 14 15 16 22 17 18 19 21 24 23 20 48 47 220 nf 220 nf clampadc (from ppg) 46 45 39 44 43 42 40 37 38 41 vertical driver buffer ccd smp_clk (from dsp) v ddd v dda1 v dda1 v dda1 v dda1 - xxv + xxv switch mode power supplies (optional) ccdout ofd level (optional) 1 m f a b c d e f g h i j k l m 5 6 7 8 2 vd (from ppg) 3 4 5 10 m f 4 3 2 1 sda scl ptc v dd a2 100 nf nc wp v ss 6 7 8 9 4.7 m f 12 mhz a0/sn da scl/sn cl hd (opt.) fi in a1/sn res 10 11 83c54/ 83c654 (om-xxx) micro- controller eprom pcf8598 pcf8594 pcf8582 13 14 15 16 17 18 19 20 21 22 18 pf 18 pf v dd v ddd v ddd v ddd v ddd v ddd v ddd v ddd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 reset_dsp (to dsp) p0.6/ad6 p0.7/ad7 ea ale psen p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 44 43 42 41 oen (optional) (to adc) bc848c 40 39 38 37 36 35 33 32 31 30 29 28 27 26 25 24 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6/scl p1.7/sda rst p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 v ss 5 v v dda1 5 v v dda2 5 v v dda3 v ddd 4jb 3jb 2jb 1 + 5 v gnd scl sda jb 10 k w 4.7 k w 4.7 k w 10 k w mgk393 digital ground analog ground shutter reset
1997 jun 13 29 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G fig.19 SAA8110G system configuration for camera application (continued from fig.18). handbook, full pagewidth mgk394 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 SAA8110G digital signal processor 12 14 16 18 20 10 nf 100 nf 100 nf 100 nf 100 nf 100 nf smp_clk (to power supply) p0 digital ground analog ground p1 reset_dsp (from m c) 21 v dda2 v dda3 v dda3 v dda3 v dda3 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 68 w 68 w 68 w 47 k w 150 k w 38 39 40 80 79 100 nf a1/sn res a0/sn da sda optional scl/sn cl 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 58 56 54 52 50 48 46 44 42 59 57 55 53 51 49 47 45 43 41 cvbs-rca cvbs v, red u, blue c green y svhs 3 4 1 2 3 4 5 11 12 13 14 15 6 7 8 9 10 1 2 6 7 5 v ddd(c1) vsync in vd fi in fi ccd9 ccd7 ccd5 ccd3 ccd1 v ssd(c2) v ddd v ddd v ssa(cd) clk1 clk1 hsync in hd v ssd(c1) v ddd ccd8 ccd6 ccd4 ccd2 ccd0 sclk cdac rbias v dda(cd) sdata strobe smp p0 p1 sis v ddd(c2) reset t2 t1 t0 v ssa(ob) out3 v dda(o3) out2 v dda(o2) out1 v dda(o1) cdac out cdac out uv1 100 nf 100 nf uv7 llc href fi out v ddd(p1) rbias v ssa(bg) uv2 uv3 uv4 uv5 uv6 v ssd(p1) v ddd(p2) v ddd v ddd cref/pxq vsync out clk2 clk2 (from ppg) v dda(bg) decoupl 100 nf 100 nf 100 nf v dda(dc) x out a0/sn da v ddd(c3) y0 y2 y4 y6 x in v ssd(c4) scl/sn cl v ssd(c3) sda a1/sn res v ssd(p2) y1 y3 y5 y7 uv0 v ddd v ddd v ddd 26 24 22 20 18 16 digital output connector 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 l (1) l (1) l (1) l (1) l (1) l (1) l (1) l (1) l (1) a b c d e f g h i j k l m (1) values depend on dsp output configuration.
1997 jun 13 30 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.16 0.04 1.5 1.3 0.25 0.25 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 0.70 0.58 1.45 1.05 4 0 o o 0.15 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.3 sot315-1 92-03-24 95-12-19 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p q detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
1997 jun 13 31 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 jun 13 32 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 jun 13 33 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G notes
1997 jun 13 34 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G notes
1997 jun 13 35 philips semiconductors preliminary speci?cation digital signal processor (dsp) for cameras SAA8110G notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca54 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 547047/1200/01/pp36 date of release: 1997 jun 13 document order number: 9397 750 01576

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